VHDL Implementation of Evolutionary Algorithm in the Evolutionary Design of Combinational Circuits

Now a days space vehicles and other electronic hardware also demands that the architectures should be small, speed in operation, low power consumption, small in area and be reconfigurable in unexpected environments. The evolvable hardware (EHW) or evolutionary algorithm used to design the desired circuit automatically. Genetic algorithm is the commonly used evolutionary algorithm. EHW, because of its binary representation, which matches perfectly with the configuration bits used in FPGA. The use of reconfigurable FPGA system will reduce the time required to re-design the system each and every time. The paper discuss about the Cartesian genetic programming for the proposed adder evolvable unit.